ASIC and FPGA design and verification
From environment design to documentation, our seasoned engineers work quickly to help you get it done right. Including high-level architecture and chip design, verification environment design, RTL coding, test case development and physical design.
Design and Verification Capabilities
Expertise
- ASIC, FPGA, SoC, partial reconfig, virtual ASSP
- RTL design: Verilog, VHDL, System Verilog
- Verification: UVM/OVM/VMM, Specman
- Verification environment creation
- Physical Design (Custom Layout, Place’n’Route, Physical Verification)
- C / C++, System C, Python
- Co-design (ARM, MIPS)
- Automation tools
- Firmware design
- Processor development
Protocols
- OTN
- Ethernet
- FlexE
- SONET
- GPONAXI4 bus
- PCIe
- SRIO
- RapidIO
- LTE/Wimax DSP design
Tools and vendors
- Xilinx, Altera
- Vivado, Quartus
- Linux, VxWorks
- Mentor tools
- Synopsys tools
How can you engage us?
We offer flexible engagement models to meet the needs of your project. This can include any or all of the following:
• Traditional on-site team augmentation • Turnkey chip development • IP block design and verification